1. Field of the Invention
The present invention relates to a semiconductor fabrication process. More particularly, the present invention relates to a method of reducing pattern pitch.
2. Description of the Related Art
As the level of integration of integrated circuits continues to increase, the size of each semiconductor device and the distance between the devices in integrated circuits must be reduced. In other words, the minimum pattern pitch, the sum of pattern line-width and the space in an integrated circuit, must be as fine as possible. At present, the minimization of pattern pitch in integrated circuit fabrication is primarily driven by getting a finer photolithographic resolution. However, advances in photographic resolution have become increasingly challenging and costly due to intrinsic optical limitations, increasingly challenging and costly due to intrinsic optical limitations. The 248-nm lithography, coupled with other resolution enhancement techniques, cannot be extended far beyond the 100-nm process technology node. The 193-nm lithography, cannot be extended far beyond the 70-nm technology node. The skyrocketing cost of photo-mask and resist for the 193-nm lithography further limits its wide applications. Further reduction in the minimum pitch in integrated circuits is thus more difficult after reaching certain photographic resolution limit. Without further reduction in pattern pitch, increasing the device packing-density and the level of integration of integrated circuits is virtually impossible. Alternative cost-effective approaches are desired.